1. Field of the Invention
The present invention relates to a step-up circuit and a semiconductor device employing same.
2. Description of the Related Art
In a semiconductor integrated circuit, along with the minuteness of circuit elements and large-scale circuits, power-supply voltages are being lowered, and different power-supply voltages are being used to power multiple semiconductor devices mounted on printed circuit boards.
In the semiconductor device LSI1 of FIG. 6(A), for example, an internal circuit 1 as a mainframe circuit operates with a power-supply voltage of Vii=2.4 V. To standardize the power-supply voltage supplied to the various semiconductor devices, an external power-supply voltage of Vcc=3.0 V is stepped down to an internal voltage of Vii by an nMOS transistor 2. Gate potential Vgn is generated at a control circuit (not shown) and provided to the gate electrode of the nMOS transistor 2 to make the internal voltage Vii constant. By using a pMOS transistor, external power-supply voltage Vcc can be used in the control circuit. However, since gate potential Vgn is about 3.3 V, which is higher than external potential Vcc, an internal step-up circuit is required when using an nMOS transistor.
Here, when using an nMOS as the transistor 2, because it is possible to achieve higher-speed operation than when using a pMOS transistor, the internal power-supply voltage can be better stabilized.
When using a pMOS as the transistor 2, because of the relationship between the inductance component of the external pin connected to the source of the transistor and the feedback control circuit for the pMOS gate potential, overdrive occurs and a back electromotive force which cannot be ignored is generated at the inductance component, causing power supply noise. When using an nMOS transistor, the relationship with the gate potential control circuit is different from the described above, and no such a problem occurs. For these reasons, it is preferred to use an nMOS as the transistor 2.
FIG. 6(B) shows part of semiconductor memory storage LSI2 as an example for another occasion requiring an internal step-up circuit. For example, when the charge stored at a capacitor 3b is transferred to a bit line BL by turning on an nMOS transistor 3a, the potential change of the bit line BL is small since the capacity of the bit line BL exceeds that of capacitor 3b. Also, the resistance of Word line WL connected to the gate electrode of the nMOS transistor 3a is considerably high. Therefore, the potential drops that may occur when the electric charge flows through nMOS transistor 3a must be minimized. So, a potential SVii provided to the word line WL through a pMOS transistor 4a of a Word driver 4 is set high. For example, the potential SVii is 4.5 V when Vii=2.4 V, and an internal step-up circuit is needed.
FIG. 7 shows a prior art step-up circuit. In this circuit, a clock is generated by a ring oscillator 10 comprising inverters 11 to 17 connected in a ring shape. This clock is provided to a charging pump circuit 20 via a buffering inverter 18. The output of ring oscillator circuit 10 is also used for On/Off control of switch elements 21 and 22. If this output is at a low level and switch elements 21 and 22 are in the status shown in the figure, a pumping capacitor 23 is charged by an output potential Vcc of the inverter 18. Next, if the output of the ring oscillator circuit 10 transits to a low level, switches 21 and 22 are respectively switched to the cathode side of diode 24 and anode side of diode 25, and the voltage of the pumping capacitor 23 is added to the external power-supply voltage Vcc. Thereby, the cathode potential V00 of the diode 25 becomes 2(Vcc-Vpn), where Vpn is a forward voltage of each diodes 24 and 25. Although the output voltage V00 is lowered according to power consumption, by repeating this step-up operations the voltage V00 can be obtained.
The charging pump circuit 20 in FIG. 7 shows the principle configuration, and actually switch elements are used instead of diodes 24 and 25 in order to reduce the drop in voltage Vpn and the switch elements are turned off during the blocking time for back flow.
When such a step-up circuit is applied to, for example, a circuit generating the gate potential Vgn of the semiconductor device LSI1 shown in FIG. 6(A) and the power is supplied to the semiconductor device LSI1, the problems as described below are encountered. Namely, since the step-up circuit will not operate until the external power supply potential Vcc reaches a specified potential, and since voltages drop due to power consumption, it takes, e.g., 400 .mu. second for the power supply voltage V00 to reach the specified value +/-10%, which delays starting operation of the internal circuit 1.
To accelerate the startup time for voltage V00 by increasing the output frequency of the ring oscillator circuit 10 will cause a load driving capacity of the step-up circuit to become unnecessarily large after startup, a power waste arising.